The present invention relates to the field of hold circuits, such as bus-hold circuits. More particularly, it relates hold circuits that may be used with power supplies of differing supply voltage.
An IGFET circuit used as a digital switch can be left with a floating input either by design or in bus applications when all devices driving the bus are in 3-state. In this state the transistors on both sides of the driving circuits are turned off leaving them with high output impedance. A floating input of an IGFET circuit allows the capacitance of the IGFET gate to gradually charge. If the gate is sufficiently charged, the resulting voltage on the gate causes static current to flow through the IGFET, causing wasted power dissipation. Further, if the gate voltage rises even further, it can reach a certain threshold where a more serious consequence can occur. In the worst case condition, it can draw enough current from the supply to ground to destroy the metal lead and render the device useless.
Initially, external static pull-up or pull-down resistors were used to prevent floating of unused gates. These static resistors connect the gate either to the supply voltage, VCC, or ground, but still cause wasted power dissipation. For bus applications where a bus driver must drive the input, bus-hold circuits have been developed. The function of a bus-hold circuit is to hold the input of the digital switch, i.e., the gate of the IGFET, to the state previously set by the bus driver. The hold must be strong enough to prevent the input from floating (charging) but weak enough to allow the input to be driven by the bus driver. Initially, these were external circuits. Now bus-hold circuits are integrated into the IGFET (including CMOS) digital IC.
In the known art, a bus-hold circuit is a digital signal feedback path from the output of a digital switch to its input, consisting of an inverter and a current-limiting resistor. The purpose of the feedback is to hold the input to its last driven state until it is driven to the alternate state. Current flows through the resistor only during the switching period when, due to propagation delays, there is a voltage difference between the output of the inverter and the input of the digital switch. Since voltage drops across the resistor occur only for brief intervals during state changes, bus-hold circuits significantly reduce the power dissipation.
The holding current through the resistor becomes the critical parameter for power dissipation by a bus-hold circuit. The magnitude of the holding current depends upon the values of the resistor and VCC. If the bus-hold circuit is used with a higher value of VCC then the magnitude of the hold override current is proportionately higher and the circuit dissipates more power in proportion to the square of the current.
Historically, the values of VCC for digital switches on IGFET integrated circuits have decreased as the state of the technology progresses. For CMOS, they have diminished from 5V to 3.3V, to 2.5V and to 1.8V. It is likely that this progression to still lower values of VCC will continue. An important benefit of evolving the technologies to operate from a lower value of VCC is that the magnitudes of the hold override currents also are reduced. That lowers the power consumption of the bus-hold circuit. This evolution to lower VCC creates the need for bus-hold circuits that can operate at two different values of VCC so it can be used with either version of the technology.
The present invention provides a hold circuit for holding a digital switch, having an input and an output, at the level of the last driven state substantially independently of the output impedance of a circuit driving the digital switch. The hold circuit includes an inverter having an input connected to the output of the digital switch and having an output, and a variable resistor having a port connected to the output of the inverter and having a port connected to the input of the digital switch.
In accordance with a preferred embodiment of the present invention, a VCC-compensated bus-hold circuit is provided that can operate from either of two adjacent values of VCC without increasing the holding currents at the higher value of VCC. This duality in circuit behavior results from introducing a variable resistor (whose resistance depends on which of the two values of VCC is applied) between the bus-hold inverter and the current limiting resistor. The dual-valued variable resistor is implemented using two transistors of different strengths connected in parallel. The transistor with the smaller channel width and therefore higher resistance is biased on continuously. When the lower value of VCC is applied, the transistor with the larger channel width and therefore lower resistance is also turned on and the parallel combination has a lower resistance. When the higher value of VCC is applied, the transistor with the larger channel width is turned off and the parallel combination then has a higher resistance. A bias circuit with VCC as input supports the operation of this embodiment. This bias circuit uses the VCC value to control the state (ON or OFF) of that transistor in the parallel pair that has the larger channel width. If the lower value of VCC is applied then the transistor with the larger channel width is turned on and the resistance is lowered. If the higher value of VCC is applied then that transistor is turned off and the resistance is increased to a value that keeps the magnitudes of the holding currents approximately the same as for the lower value of VCC.